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nb650/nb650h high-effeciency, fast-transient, 6a, 28v synchronous step-down c onverters with 2-bit vid nb650/nb650h rev. 1.12 www.monolithicpower.com 1 10/11/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. the future of analog ic technology description the nb650/nb650h is fully-integrated, high- frequency, synchronous, rectified, step-down, switch-mode converters with dynamic-output? voltage control. it offers a very compact solution to achieve 6a of continuous output current over a wide input supply range, and has excellent load and line regulation. the nb650/nb650h operates at high efficiency over a wide output- current?load range. constant-on-time control mode provides fast transient response and eases loop stabilization. 2-bit vid inputs support changing the output voltage on-the-fly. full protection features include short-circuit protection, over-current protection, over-voltage protection, under-voltage protection, and thermal shut down. the nb650/nb650h requires a minimal number of readily-available standard external components, and is available in a space-saving 3mm4mm qfn17 package. features ? wide 4.5v-to-28v operating input range ? 6a output current ? internal 50m ? high-side, 18m ? low-side power mosfets ? proprietary switching loss reduction technique ? 1% reference voltage ? programmable soft-start time ? 2-bit vid input ? soft shutdown ? frequency programmable from 150khz to 1mhz ? scp, ocp, ovp, uvp, and thermal shutdown ? optional ocp protection: latch-off mode (nb650) and hiccup mode (nb650h) ? output adjustable from 0.6v to 13v ? available in qfn17 (3mm4mm) package applications ? notebook systems and i/o power ? networking systems ? digital set top boxes ? flat-panel televisions and monitors ? distributed power systems all mps parts are lead-free and adhere to the rohs directive. for mps green status, please visit mps website under quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithi c power systems, inc. typical application for notebook in freq vcc en pgnd bst fb sw nb650 nb650h v in on/off c1 r7 r6 c5 c3 l1 r4 c4 r1 r2a c2 r5 on/off on/off pg vid1 vid2 gnd rfb2 rfb1 ss r2b r2c v out c6 11 17 5 8 4 6 716 9,10 12 15 14 13 1,2 3
nb650/nb650h ? 6a, 28v, fast-transient, synchronous step-down converters nb650/nb650h rev. 1.12 www.monolithicpower.com 2 10/11/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. ordering information part number package top marking NB650GL * nb650 nb650hgl ** qfn17 (3 x 4mm) nb650h * for tape & reel, add suffix ?z (e.g. NB650GL?z) ** for tape & reel, add suffix ?z (e.g. nb650hgl?z) package reference top view sw sw in gnd gnd bst pg en vid1 vid2 vcc agnd ss freq rfb1 fb rfb2 in gnd gnd sw sw 1 2 34 8 7 6 5 9 10 11 12 13 14 15 16 17 exposed pad on backside qfn17 (3x4mm) absolute maxi mum ratings (1) supply voltage v in ....................................... 28v v sw ........................................-0.3v to v in + 0.3v v sw ..............................-3v to v in + 3v for <30ns v bst ...................................................... v sw + 6v all other pins ..................................-0.3v to +6v continuous power dissipation (t a = +25c) (2) qfn17 ?.????????? ???.2.4w junction temperature ...............................150c lead temperature ....................................260c storage temperature............... -65c to +150c recommended operating conditions (3) supply voltage v in ........................4.5v to 22.5v output voltage v out .........................0.6v to 13v operating junction temp. (t j ). -40c to +125c thermal resistance (4) ja jc qfn17(3 x 4mm) ....................52 .... 11 .. c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature ta. the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max)=(t j (max)- t a )/ ja . exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb.
nb650/nb650h ? 6a, 28v, fast-transient, synchronous step-down converters nb650/nb650h rev. 1.12 www.monolithicpower.com 3 10/11/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. electrical characteristics v in = 12v, t j = +25c, unless otherwise noted. parameters symbol condition min typ max units input supply current (shutdown) i in v en = 0v 0 a input supply current (quiescent) i in v en = 2v, v fb =0.65v 400 a switch leakage sw lkg v en = 0v, v sw = 0v or 12v 0 1 a current limit i limit t on >200ns 8 10 a one-shot on time t on r freq =200k ? , v out =1.2v 200 ns minimum off time t off r freq =200k ? 100 ns fold-back off time (5) t fb ilim=1 1.2 s ocp hold-off time (5) t oc ilim=1 50 s feedback voltage v fb 594 600 606 mv feedback current i fb v fb = 600mv 10 100 na soft start charging current i ss v ss =0v 10 a soft stop charging current i ss v ss =0.6v 10 a en input low voltage vil en 0.4 v en input high voltage vih en 2 v v en = 2v 1.5 en input current i en v en = 0v 0 a ovp feedback threshold v fb-ov 0.8 v uvp feedback threshold (5) v fb-uv 0.4 v vid inputs low voltage vil vid 0.4 v vid inputs high voltage vih vid 2 v vid inputs current i vid 0 a equivalent fb slew rate during vid on-the-fly (5) sr fb 20 mv/ s vid switch on resistance (5) vid rds-on 100 ? power good rising threshold pg vth-hi 0.9 v fb power good falling threshold pg vth-lo 0.85 v fb power good delay pg td 0.5 ms power good sink cu rrent capability v pg sink 4ma 0.4 v power good leakage current i pg_leak v pg = 3.3v 10 na standby mode delay time (5) t standby 12 s v in under voltage lockout threshold rising inuv vth 4 v v in under voltage lockout threshold hysteresis inuv hys 800 mv thermal shutdown (5) t sd 150 c note: 5) not tested. not guaranteed.
nb650/nb650h ? 6a, 28v, fast-transient, synchronous step-down converters nb650/nb650h rev. 1.12 www.monolithicpower.com 4 10/11/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. pin functions qfn17 pin # name description 1,2 sw switch output. conne ct using wide pcb traces. 3 bst bootstrap. requires a capacitor between sw and bst to form a floating supply across the high-side switch driver. 4 pg power good. output is an open drain and is high if the output voltage exceeds 90% of the nominal voltage. there is a delay from fb 90%v ref to pg goes high. 5 en en=1 to enable. for automatic start-up, connect to vin with a 100k ? resistor. 6,7 vid1 vid2 vid inputs. control signals for the output-volt age scaling. acts as the control signals for the internal vid switches. usually uses an exte rnal resistor in parallel with the low-side fb resistor. changing the vid on/off state changes the fb divider scaling and result in different output voltages. 8 vcc internal ldo output. the power supply of the internal control circuits. decouple with 1 f capacitor. 9,10 gnd system ground. the reference ground of the regulated output voltage. layout requires extra care. 11 in supply voltage. operates from a 4.5v-to-28v input rail. requires c1 to decouple the input rail. connect using wide pcb traces. 12 agnd analog ground. 13 fb feedback. connect to the tap of an external resistor divi der from the output to gnd to set the output voltage. 14,15 rfb2 rfb1 drain of the internal vid switches. typically us es an external resistor in parallel with the low-side fb resistor along with the inter nal vid switch to change the on/off state of the vid switching to change the fb divider scaling and result in different output voltages. 16 ss soft-start. connect an external capacitor to program the soft-start time for the switch- mode regulator. 17 freq frequency set during ccm. the input voltage and the frequency-set resistor between the in and freq pin determines the on period. for best results, use an on period longer than 200ns. decouple with a 1nf capacitor.
nb650/nb650h ? 6a, 28v, fast-transient, synchronous step-down converters nb650/nb650h rev. 1.12 www.monolithicpower.com 5 10/11/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics v in =12v, v out =1.05v, l=1h, t a =+25c, unless otherwise noted.
nb650/nb650h ? 6a, 28v, fast-transient, synchronous step-down converters nb650/nb650h rev. 1.12 www.monolithicpower.com 6 10/11/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics (continued) v in =12v, v out =1.05v, l=1h, t a =+25c, unless otherwise noted.
nb650/nb650h ? 6a, 28v, fast-transient, synchronous step-down converters nb650/nb650h rev. 1.12 www.monolithicpower.com 7 10/11/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics (continued) v in =12v, v out =1.05v, l=1h, t a =+25c, unless otherwise noted. v out 500mv/div. v en 5v/div. v sw 10v/div. i l 2a/div. v out 500mv/div. v en 5v/div. v sw 10v/div. i l 10a/div. v out (ac) 50mv/div. v sw 10v/div. i l 5a/div. v out 500mv/div. v sw 10v/div. i l 5a/div. v out 500mv/div. v sw 10v/div. i l 5a/div. v out 500mv/div. v en 5v/div. v sw 10v/div. i l 10a/div. v out 500mv/div. v en 5v/div. v sw 10v/div. i l 2a/div. start-up through en i out = 0a start-up through en i out = 6a shutdown through en i out = 0a shutdown through en i out = 6a short circuit protection nb650, latch-off version ocp protection nb650, latch-off version vid1 5v/div. vid2 5v/div. vid1 5v/div. vid2 5v/div. vid on-the-fly i out = 0.3a f vid1 = 1khz, f vid2 = 0.5khz, v out = 1.05v/1.1v/1.15v/1.2v v out (ac) 100mv/div. v out (ac) 100mv/div. vid on-the-fly i out = 6a f vid1 = 1khz, f vid2 = 0.5khz, v out = 1.05v/1.1v/1.15v/1.2v
nb650/nb650h ? 6a, 28v, fast-transient, synchronous step-down converters nb650/nb650h rev. 1.12 www.monolithicpower.com 8 10/11/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. functional block diagram freq oc pgood comparator pgood bst - + vcc uv detect comparator - + 5v ldo 0.4 v ilim uv ov hs_mos 1m eg ls_mos rsen 0 0 vcc 0 ov detect comparator + - 0.8v pwm agnd logic off timer current modulator bstreg soft start/stop loop comparator - + + xs xr hs driver q cur r e nt se nse amplifer sw - + ls driver gnd en in reference 0.6v start fb refresh timer ss hs ilimit comparator - + on timer over-current timer 0 0 drain1 vid1 drain2 vid2 mux1 mux2 1 2 1 2 vidsl figure 1: functional block diagram
nb650/nb650h ? 6a, 28v, fast-transient, synchronous step-down converters nb650/nb650h rev. 1.12 www.monolithicpower.com 9 10/11/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. operation pwm operation the nb650/nb650h is a fully-integrated, synchronous, rectified, step-down, switch-mode converter with dynamic output voltage control. it offers a very compact solution to achieve a 6a continuous output current over a wide input supply range, with excellent load and line regulation. the nb650/nb650h operates at high efficiency over a wide output current load range. constant-on-time (cot) provides a fast transient response and easy loop stabilization. at the beginning of each cycle, the high-side mosfet (hs-fet) turns on when the feedback voltage (v fb ) falls below the reference voltage (v ref ), which indicates an insufficient output voltage. the input voltage and the frequency-set resistor determine the on as follows: freq on delay1 in 9.6 r (k ) t(ns) t (ns) v(v) 0.4 =+ ? (1) where t delay1 is the 20ns delay of a comparator in the t on module. for best results, select t on 120ns. after the on period elapses, the hs-fet turns off to enter the off state. the part turns on again when v fb drops below v ref . by repeating this operation, the converter regulates the output voltage. the integrated low-side mosfet (ls- fet) turns on when the hs-fet is off to minimize conduction loss. there is a dead short between input and gnd (shoot-through) if both hs-fet and ls-fet turn on at the same time. an internally-generated dead-time (dt) between hs-fet off and ls-fet on, or ls-fet off and hs-fet off avoids shoot-through. heavy-load operation as shown in figure 2, the hs-fet and ls-fet repeatedly turn on/off when the output current is high, and the inductor current never goes to zero. it?s called continuous-conduction-mode (ccm) operation. in ccm operation, the switching frequency (f sw ) is fairly constant. figure 2: heavy-load operation light-load operation when the load current decreases, the nb650/nb650h automatically reduces the switching frequency to maintain high efficiency. figure 3 shows the light-load operation. v fb does not reach v ref when the inductor current approaches zero. as the output current drops from heavy-load condition, the inductor current also decreases and eventually approaches zero. the ls-fet driver enters a tri-state (high-z) whenever the inductor current reaches zero. a current modulator takes control of the ls-fet and limits the inductor current to less than 600 a to slowly discharge the output capacitors to gnd through ls-fet as well as r1 and r2a, r2b and r2c. the hs-fet does not turn on as frequently as in heavy-load condition. as a result, the efficiency at light-load condition increases greatly. this operation mode is also called skip mode. figure 3: light-load operation as the output current increases from the light- load condition, the time period within which the current modulator regulates becomes shorter. as the part exits light-load mode, the hs-fet turns on more frequently to increase the switching frequency. the output current reaches critical when the current modulator time is zero. the
nb650/nb650h ? 6a, 28v, fast-transient, synchronous step-down converters nb650/nb650h rev. 1.12 www.monolithicpower.com 10 10/11/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. following equation determines the critical level of the output current: in out out out sw in (v v ) v i 2lf v ? = (2) when the output current exceeds the critical level, light load mode turns into pwm mode, and the switching frequency stays fairly constant over the output current range. switching frequency the nb650/nb650h uses constant-on-time (cot) control, and has no dedicated internal oscillator. the input voltage is feed-forwarded to the on-time one-shot timer through the resistor r freq . the duty ratio is kept as v out /v in . hence, the switching frequency is fairly constant over the input voltage range. the switching frequency can be set as follows: 6 1 2 1 10 4 0 6 9 ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + ? = ? ) ns ( t ) v ( v ) v ( v ) ns ( t . ) v ( v ) k ( r . ) khz ( f delay out in delay in freq sw (3) where t delay2 is another comparator delay of about 40ns. figure 4: plot of v out as a function of r freq and the frequency nb650/nb650h is optimized to operate at high switching frequencies at high efficiency. higher switching frequencies allow for smaller lc filter components to reduce system pcb space. jitter and fb ramp slope figure 5 and figure 6 show jitter in both pwm and skip modes. when there is noise in the v fb downward slope, the on time of hs-fet deviates from its intended level and produces jitter. there is a relationship between a system?s stability and the steepness of the v fb ripple?s downward slope: the steepness of the v fb ripple?s slope dominates in noise immunity. the magnitude of the v fb ripple doesn?t directly affect the noise immunity. figure 5: jitter in pwm mode figure 6: jitter in skip mode ramp with large esr cap when using poscaps or other types of capacitors with larger esr as output capacitors. the esr ripple dominates the output ripple, and the slope on the fb is esr-related. figure 7 shows an equivalent circuit in pwm mode with the hs-fet off and without an external ramp circuit. the application section includes design steps for large esr capacitors.
nb650/nb650h ? 6a, 28v, fast-transient, synchronous step-down converters nb650/nb650h rev. 1.12 www.monolithicpower.com 11 10/11/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. figure 7: simplified circuit in pwm mode without external ramp compensation to realize the stability without the use of an external ramp, select an esr value as follows: sw on esr out tt 0.7 2 r c + (4) where t sw is the switching period. ramp with small esr capacitor the esr ripple when using ceramic output capacitors is not high enough to stabilize the system and requires an external compensation ramp. the application section includes a description of designing with small esr capacitors. figure 8: simplified circuit in pwm mode with external ramp compensation figure 7 shows a simplified equivalent circuit in pwm mode with the hs-fet off and an external ramp compensation circuit (r4, c4). the external ramp is derived from the inductor ripple current. if one chooses c4, r9, r1 and r2 to meet the following condition: 12 9 sw 4 1 2 rr 11 r 2f c 5rr ?? < + ?? + ?? (5) where: r4 c4 fb c4 iiii =+ (6) and r2 is the equivalent resistor from fb to gnd that varies with vid input, the ramp on the v fb can then be estimated as: in o 12 ramp on 44 12 9 vv r//r vt rc r//rr ? = + (7) usually r9 is set to 0 ? , then equation 7 can be simplified as: 4 4 c r ) v v ( v on o in ramp ? = (8) the downward slope of the v fb ripple then follows out ramp slope1 off 4 4 v v v trc ? ? == (9) as shown in equation 8, if there is instability in pwm mode, we can reduce either r4 or c4. if c4 can not be reduced further due to limitations from equation 5, then we can only reduce r4. for a stable pwm operation, the v slope1 should be designed as follows. 3 10 sw on esr out slope1 out out sw on tt +-rc io 0.7 2 -v v + 2lc t -t ? (10) where i o is the load current. in skip mode, the downward slope of the v fb ripple is almost the same with or without the external ramp. figure 9 shows the simplified circuit of the skip mode when both hs-fet and ls-fet are off. figure 9: simplified circuit in skip mode the downward slope of the v fb ripple in skip mode can be determined as: () ref slope2 12 out v v (r r //ro) c ? = + (11)
nb650/nb650h ? 6a, 28v, fast-transient, synchronous step-down converters nb650/nb650h rev. 1.12 www.monolithicpower.com 12 10/11/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. where r o is the equivalent load resistor. as described in figure 6, v slope2 in skip mode is smaller than v slope1 in pwm mode, so the jitter in the skip mode is larger. for less jitter during ultra-light?load conditions, select smaller v fb resistors, though at the cost of light-load efficiency. vid input typically, r1 and r2 set the output voltage with v fb =0.6v. r2, in this case, is a combination of r2a, r2b, and r2c depends on the vid, which is active low. the nb650/nb650h can dynamically track vid codes as they change. as a result, the converter output voltage can change without the need to reset either the controller or the value of r1 and r2a. as shown in figure 1, r2b and r2c are parallel with r2a. the equivalent value of r2 can change due to different vid codes. one can get four v out values depending on the vid codes with the details in the application information. the vid logic and equivalent r2s are shown in table 1. table 1: vid logic 2 vid 1 vid r2 1 1 22a rr = 1 0 22a2b rr//r = 0 1 22a2c rr//r = 0 0 22a2b2c rr//r//r = enable control the nb650/nb650h has a dedicated enable control pin (en). pulling this pin high or low enables or disables the ic. tie en to v in through a resistor for automatic start-up. soft start/stop the nb650/nb650h employs a soft-start/stop (ss) mechanism to ensure smooth output during power-up and power shutdown. when the en pin goes high, an internal current source (10 a) charges up the ss capacitor. the ss capacitor voltage then acts as the v ref voltage to the pwm comparator. the output voltage smoothly ramps up with the ss voltage. once the ss voltage reaches the same level as the ref voltage, it continues ramping up while the ref voltage becomes the reference to the pwm comparator. at this point, the soft-start finishes and it enters steady-state operation. when the en pin goes low, a 10a internal current source discharges the ss capacitor. once the ss voltage reaches the ref voltage, acts as the reference to the pwm comparator. the output voltage decreases smoothly with the ss voltage until it reaches zero level. determine the ss capacitor as follows: ) v ( v ) a ( i ) ms ( t ) nf ( c ref ss ss ss = (12) if the output capacitors have large capacitance values, avoid setting a short ss time. use a minimum value of 4.7nf if the output capacitance value exceeds 330f. power good the nb650/nb650h has power-good (pg) output. the pg pin is the open drain of a mosfet. connect to v cc or another voltage source through a resistor (e.g. 100k ? ). the mosfet turns on after the application of the input voltage so that the pg pin is pulled to gnd before the ss is ready. after the fb voltage reaches 90% of the reference voltage, the pg pin is pulled high after a delay. the pg delay is determined as follows: 9 4 ) ms ( t ) ms ( t ss pg = (13) when the fb voltage drops to 90% of the reference voltage, the pg pin is pulled low. over-current protection and short-circuit protection the nb650/nb650h has cycle-by-cycle over- current limit control. the inductor current is monitored during the on state. once the inductor current hits the current limit, the hs-fet turns off. at the same time, the over-current protection (ocp) timer starts. the ocp timer is set as 50 s. if the current limit is hit for every cycle within that 50 s period, then ocp will trigger. when the output is shorted to ground, the device hits its current limit and the fb voltage is less than 0.4v. the device treats this as a dead-short
nb650/nb650h ? 6a, 28v, fast-transient, synchronous step-down converters nb650/nb650h rev. 1.12 www.monolithicpower.com 13 10/11/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. on the output and triggers ocp immediately. this is short circuit protection (scp). under ocp/scp condition, nb650 will latch off. the converter needs power cycle to restart. nb650h will try to recover from ocp/scp fault with hiccup mode. that means in ocp/scp protection, the nb650h will disable the output power stage, discharge soft-start capacitor and then automatically try to start again. if the over- current condition still holds after soft-start ends, the nb650h repeats this operation cycle till over- current fault is removed and output rises back to regulation level. over/under-voltage protection the nb650/nb650h monitors the output voltage through the fb voltage to detect overvoltage and under voltage on the output. when the fb voltage exceeds 0.8v, the over-voltage protection (ovp) triggers. once ovp triggers, the ls-fet is always on while the hs-fet is always off. the device needs to power cycle to power up again. under-voltage protection (uvp) triggers when the fb voltage is below 0.4v. usually, uvp accompanies hitting the current limit, which results in scp. uvlo protection the nb650/nb650h has under-voltage lockout (uvlo) protection. when v in exceeds the uvlo- rising threshold voltage, the nb650/nb650h powers up. it shuts off when v in falls below the uvlo-falling threshold voltage. this is non-latch protection. thermal shutdown the nb650/nb650h employs thermal shutdown by internally monitoring the temperature of the junction. if the junction temperature exceeds the threshold value (typically 150c), the converter shuts off. this is non-latch protection. there is about 25c hysteresis. once the junction temperature drops to around 125c, it initiates a soft-start.
nb650/nb650h ? 6a, 28v, fast-transient, synchronous step-down converters nb650/nb650h rev. 1.12 www.monolithicpower.com 14 10/11/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. application information setting the output voltage-large esr caps a resistor divider from the output voltage to the fb pin sets the output voltage. changing the vid codes for the nb650/nb650h accomplishes the same thing. when there is no external ramp, the output voltages are set by feedback resistors r1 and r2a, r2b and r2c. first, choose r1 within 5k ? - to-100k ? to ensure stable operation. v out1 , v out2 , v out3 and v out4 are the voltages at different vid codes, arranged from low to high. then determine r2a, r2b and r2c as follows: ref 1 out1 out ref 2 v r2a r1 vvv = ? ? (14) 1 out2 out2 ref 2 ref 1 r2b vvv 11 vr1r2a = ? ? ? (15) 1 out3 out3 ref 2 ref 1 r2c vvv 11 vr1r2a = ? ? ? (16) v out4 can be calculated as: ref 1 out4 out4 2 v (r1 r2a // r2b // r2c) vv r2a // r2b // r2c + =+ (17) where out x v is the output ripple determined by equation 30 . setting the output voltage-small esr caps figure 10: simplified ceramic capacitor circuit when using a low-esr ceramic capacitor on the output, add an external voltage ramp to fb through resistor r4 and capacitor c4. the ramp voltage, v ramp , influences the output voltage besides the resistor divider shown in figure 10. equation 7 calculates v ramp . choose r1 within 5k ? -to-100k ? . the value of r2 then is determined as follows: ) v (v ) r9 r4 1 r1 1 ( v r2a fb(avg) out1 fb(avg) ? + + = (18) r2a 1 r9 r4 1 r1 1 v v v 1 r2b fb(avg) fb(avg) out2 ? + + ? = ) ( (19) r2a 1 r9 r4 1 r1 1 v v v 1 r2c fb(avg) fb(avg) out3 ? + + ? = ) ( (20) and v out4 also can be calculated with equation 17. the v fb(avg) is the average value on fb. v fb(avg) varies with the v in , v o , and load condition; its value in skip mode is lower than in pwm mode, which means the load regulation is strictly related to the v fb(avg) . also the line regulation is related to the v fb(avg) ; use a lower v ramp that meets the conditions of equation 10 for better load or line regulation. for pwm operation, estimate v fb(avg) from the following equation: r9 r1//r2 r1//r2 v 2 1 v v ramp ref fb(avg) + + = (21) usually, r9 is set to 0 ? , and it can also be set following equation 22 for better noise immunity. set the value to <(1/5)r1//r2 to minimize its influence on v ramp . sw 2f c4 2 1 r9 (22) using equations 18 through 20 to calculate the output voltage can be complicated. furthermore, as v ramp changes due to changes in v out and v in , v fb also varies. to improve the output voltage accuracy and simplify the r2a, r2b and r2c calculations, add a dc-blocking capacitor (c dc ) to filter the dc influence from r4 and r9. figure 11 shows a simplified circuit with external ramp compensation and a dc-blocking capacitor. the addition of this capacitor simplifies the r2a, r2b and r2c calculations, as per equations 23-25.
nb650/nb650h ? 6a, 28v, fast-transient, synchronous step-down converters nb650/nb650h rev. 1.12 www.monolithicpower.com 15 10/11/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. ) v 2 1 v (v r1 1 v 2 1 v r2a ramp ref out1 ramp ref ? ? + = (23) r2a 1 v 2 1 v ) v 2 1 v (v r1 1 1 r2b ramp ref ramp ref out2 ? + ? ? = (24) r2a 1 v 2 1 v ) v 2 1 v (v r1 1 1 r2c ramp ref ramp ref out3 ? + ? ? = (25) select c dc >10c4 for better dc blocking, but select a value less than 0.47f when considering start up performance. for larger c dc values for better fb noise immunity, combine with reduced r1 and r2 to limit the c dc to a reasonable value without affecting system start-up. note that even with c dc , the load and line regulation are still related to v ramp . figure 11: simplified circuit with ceramic dc- blocking capacitor input capacitor the input current to the step-down converter is discontinuous, and therefore requires a capacitor to supply the ac current to the step-down converter while maintaining the dc input voltage. use ceramic capacitors for best performance. the capacitance varies significantly over temperature. capacitors with x5r and x7r ceramic dielectrics are recommended because they are fairly stable over temperature. in the layout, place the input capacitors as close to the in pin as possible. the capacitors must also have a ripple current rating greater than the maximum input ripple current of the converter. the input ripple current can be estimated as: out out cin out in in vv ii (1 ) vv = ? (26) the worst-case condition occurs at: out cin i i 2 = (27) for simplification, choose an input capacitor whose rms current rating is greater than half of the maximum load current. the input capacitance value determines the input voltage ripple of the converter. if the system requires a specific input voltage ripple, choose the input capacitor that meets the specification. the input voltage ripple can be estimated as: out out out in sw in in in iv v v(1) fc v v = ? (28) the worst-case condition occurs at v in = 2v out , where: out in sw in i 1 v 4f c = (29) output capacitor the output capacitor maintains the dc output voltage. use ceramic or poscap capacitors. the output voltage ripple can be estimated as: out out out esr sw in sw out vv 1 v(1)(r ) fl v 8fc = ? + (30) where r esr is the equivalent series resistance (esr) of the output capacitor. for ceramic capacitors, the capacitance dominates the impedance at the switching frequency, and causes the majority of the output voltage ripple. for simplification, the output voltage ripple can be estimated as: out out out 2 in sw out vv v(1) v 8f lc = ? (31) the output voltage ripple caused by esr is very small, and therefore requires an external ramp to stabilize the system. the external ramp can be generated through resistor r4 and capacitor c4 following equations 5, 9 and 10. for poscap capacitors, the esr dominates the impedance at the switching frequency. the ramp voltage generated from the esr is high enough to stabilize the system. therefore, an external
nb650/nb650h ? 6a, 28v, fast transient synchronous step-down converter nb650/nb650h rev. 1.1 www.monolithicpower.com 16 10/11/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. ramp is not needed. a minimum esr value of 12m ? is required to ensure stable operation of the converter. for simplification, the output ripple can be approximated as: out out out esr sw in vv v(1)r fl v = ? (32) inductor the inductor supplies constant current to the output load while being driven by the switching input voltage. a larger value inductor results in less ripple current, which results in lower output ripple voltage. however, a larger value inductor is physically larger, has a higher series resistance, and/or lower saturation current. to determine the inductor value, allow the inductor peak-to-peak ripple current to reach approximately 30% to 40% of the maximum switch current limit. make sure that the peak inductor current is below the maximum switch current limit. the inductance value can be calculated as: out out sw l in vv l(1) fi v =? (33) where i l is the peak-to-peak inductor ripple cur rent. choose an inductor that will not saturate under the maximum inductor peak current. the peak inductor current can be calculated as: out out lp out sw in vv ii (1 ) 2f l v =+ ? (34)
nb650/nb650h ? 6a, 28v, fast-transient, synchronous step-down converters nb650/nb650h rev. 1.12 www.monolithicpower.com 17 10/11/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical application v in r7 205k 11 3 1, 2 13 14 15 16 12 9, 10 17 5 8 4 6 7 r5 100k c7 1nf nb650 nb650h in freq vcc pg en ss pgnd gnd fb rfb1 rfb2 sw bst r2a 16.5k r1 12.1k r3 4.7 v out r2c 73.2k r2b 143k vid1 vid2 r10 1meg sw1 r11 1meg r6 100k c6 100nf figure 12: typical application circuit with no external ramp v in = 12v, v out = 1.05/1.15/1.20v, i out = 6a, f sw = 550khz v in r7 205k 11 3 1, 2 13 14 15 16 12 9, 10 17 5 8 4 6 7 r5 100k c7 1nf nb650 nb650h in freq vcc pg en ss pgnd gnd fb rfb1 rfb2 sw bst r2a 16k r1 12.1k r3 4.7 r2c 69.8k r2b 140k vid1 vid2 r10 1meg sw1 r11 1meg r6 100k c6 100nf r9 0 r4 274k c4 330pf v out figure 13: typical application with low-esr ceramic capacitor v in = 12v, v out = 1.05/1.10/1.15/1.20v, i out = 6a, f sw = 550khz
nb650/nb650h ? 6a, 28v, fast-transient, synchronous step-down converters nb650/nb650h rev. 1.12 www.monolithicpower.com 18 10/11/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. v in r7 205k 11 3 1, 2 13 14 15 16 12 9, 10 17 5 8 4 6 7 r5 100k c7 1nf nb650 nb650h in freq vcc pg en ss pgnd gnd fb rfb1 rfb2 sw bst r2a 16.9k r1 12.1k r3 4.7 r2c 73.2k r2b 147k vid1 vid2 r10 1meg sw1 r11 1meg r6 100k c6 100nf cdc 100nf r4 274k c4 330pf v out figure 14: typical application circuit with low- esr ceramic capacitor and dc-blocking capacitor v in =12v, v out = 1.05/1.10/1.15/1.20v, i out = 6a, f sw = 550khz v in r7 300k 11 3 1, 2 13 14 15 16 12 9, 10 17 5 8 4 6 7 r5 100k c7 1nf nb650 nb650h in freq vcc pg en ss pgnd gnd fb rfb1 rfb2 sw bst r2a 97.6k r1 5.76k r3 4.7 r2c 23.2k r2b 34.8k vid1 vid2 r10 1meg sw1 r11 1meg r6 100k c6 100nf r9 0 r4 340k c4 330pf v out figure 15: typical application circuit v in = 19v, v out = 0.65/0.75/0.80/0.90v, i out = 6a
nb650/nb650h ? 6a, 28v, fast-transient, synchronous step-down converters nb650/nb650h rev. 1.12 www.monolithicpower.com 19 10/11/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. layout recommendations 1. place the high current paths (gnd, in, and sw) as close to the device as possible with direct, short, and wide traces. 2. use a 0.1 f input decoupling capacitor to connect the in and gnd pins. put the input decoupling capacitor and input capacitors as close to the in and gnd pins as possible. 3. put the v cc decoupling capacitor as close to the v cc and gnd pins as possible. 4. keep the switching node sw short and away from the feedback network. 5. place the external feedback resistors next to the fb pin. make sure that there is no via on the fb trace. 6. keep the bst voltage path (bst, c bst, and sw) as short as possible. 7. connect the bottom in and sw pads to large copper areas to achieve better thermal performance. 8. use a four-layer layout to achieve better thermal performance. c1 sw1 c2 l1 r3 c5 r3 r2a r3 r1 r3 r5 r3 r2c r3 r7 r3 c4 r3 r4 r3 r2b r3 c3 sw sw in pgnd pgnd bst pg en vid1 vid2 vcc agnd ss freq rfb1 fb rfb2 in pgnd pgnd sw sw 1 2 34 8 7 6 5 9 10 11 12 13 14 15 16 17 gnd vin vout sw gnd top layer inner1 layer inner2 layer bottom layer figure 16: pcb layout guide
nb650/nb650h ? 6a, 28v, fast-transient, synchronous step-down converters notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. nb650/nb650h rev. 1.12 www.monolithicpower.com 20 10/11/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. package information qfn17 (3 x 4mm) side view top view 1 17 8 2 bottom view 2.90 3.10 3.90 4.10 0.80 bsc 0.80 1.00 0.00 0.05 0.20 ref pin 1 id marking 0.80 recommended land pattern 1.00 note: 1) all dimensions are in millimeters. 2) exposed paddle size does not include mold flash. 3) lead coplanarity shall be 0.10 millimeter max. 4) jedec reference is mo-220. 5) drawing is not to scale. 0.70 0.20 0.30 pin 1 id index area 0.50 0.70 1.00 bsc 12 3 0.20 0.30 0.35 0.45 9 11 0.80 0.25 0.80 bsc 0.50 bsc 2.90 3.90 0.60 0.50 0.35 0.45 0.70 0.25

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